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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-22004-1E
ASSP Communication Control
IEEE 1394 Open HCI Controller MB86613
s DESCRIPTION
The MB86613 a high-performance, host-bus (PCI) and serial-bus (1394) controller chip for controlling transfer between the PCI and 1394 buses. This chip conforms to the PCI Standard Version 2.1 for PCI control, the IEEE 1394-1995 Standard for 1394 control, and the Open HCI Standard Version 1.0 for PCI-1394 control. The MB86613 consists of the PCI/DMA, OHCI, and 1394 blocks. The PCI/DMA block provides PCI bus protocol control. The block has the slave function for responding register access from a bus master, the master function for issuing transfer requests from the MB86613 as the bus master, the power management function (compliant with PCI bus power management standard version 1.0), and the interfaces to BIOS ROM and PCI configuration ROM. The OHCI block analyzes context programs pre-stored in host memory to store the packet to be sent out from host memory to the FIFO buffer or to store the received packet from the FIFO buffer to host memory. The 1394 block incorporates the LINK layer module, PHYsical layer module, 1394 transceiver, comparator, and PLL, providing 1394 bus protocol control. The block converts the packet stored in the FIFO buffer to serial data and send it onto the 1394 bus or converts the packet received from the 1394 bus to parallel data and stores it in the FIFO buffer. For packet transmission and reception, the chip supports a transfer rate of up to S400. In addition, the cycle master function is provided for automatic management of isochronous cycles. The chip reserves 6K bytes of FIFO memory. The on-chip dual port RAM contains 3K bytes for packet transmission and 3K bytes for packet reception. The MB86613 uses the 0.35 micron CMOS process technology, integrating the LINK and PHYsical layer modules on this single chip to reduce the packaging area and power consumption. The chip has a dual-voltage system to support both 5 V (PCI/DMA) and 3.3 V (1394) power-supply voltages. Note that the PCI/DMA block can operate at 3.3 V. The package is a plastic package of LQFP144 or FBGA176.
s PACKAGES
144-pin plastic LQFP 176-pin plastic FBGA
(FPT-144P-M08)
(BGA-176P-M02)
MB86613
s FEATURES
1.
* * * * * * * * * *
1394 serial bus controller Unit
Compliant with IEEE 1394-1995 Standard PHYsical and LINK layer modules integrated on a single chip Three internal ports Transfer rates of S100, S200, and S400 supported On-chip PLL for generating 400-MHz (PHY) and 50-MHz (LINK) CLK signals Built-in cycle master function Bus management CSR (control and status register) Six-conductor cable supported Internal transceiver and comparator Internal comparator for cable power detection
2.
Context program controller unit
* Compliant with Open HCI Standard (Draft 1.00) * Thirteen context program controllers integrated: Asynchronous Transmit DMA ...2ch *Asynchronous response *Asynchronous request Isochronous Transmit DMA ...4ch Receive DMA ...7ch *Asynchronous response *Asynchronous request *Isochronous *SelfID * Internal 6-KB FIFO buffers Asynchronous Transmit FIFO isochronous Transmit FIFO Asynchronous/Isochronous Receive FIFO
...1ch ...1ch ...1ch ...1ch ...4ch ...1ch
...1.5 Kbyte ...1.5 Kbyte ...3.0 Kbyte
3.
* * * * * * * * *
PCI bus controller unit
Compliant with PCI Standard (Revision 2.2) On-chip 32-bit DMA controller Built-in power management function (Compliant with PCI bus power management standard version 1.0) Built-in alignment function Built-in byte swap function Operating frequency of up to 33 MHz Internal parallel ROM interface Internal serial ROM interface Internal universal (5/3.3 V shared) PCI buffer
4.
Physical specifications
* Package: LQFP144 (FPT-144P-M08), FBGA176 (BGA-176P-M02) * Power-supply voltage: Dual system for 5 V ( 5%) and 3.3 V ( 5%)
5.
* * * * 2
Reference standards
IEEE Standard for a High Performance 1394-1995 1394 Open Host Controller Interface Specification (Release 1.00) PCI Specification (Revision 2.2) PCI Bus Power Management Interface Specification (Version 1.0)
MB86613
s PIN ASSIGNMENT
1. LQFP-144
(TOP VIEW)
AD31 AD30 AD29 AD28 AD27 VSS5/3 AD26 AD25 AD24 C/BE3# IDSEL VSS5/3 AD23 AD22 AD21 AD20 VDD5/3 DVDD3 DVSS3 AD19 AD18 AD17 AD16 VSS5/3 C/BE2# FRAME# IRDY# TRDY# DEVSEL# VSS5/3 STOP# PERR# SERR# PAR C/BE1# VDD5/3 135 140 144 130 125 115 109 110 120 1
AD15 AD14 AD13 AD12 AD11 VSS5/3 AD10 AD9 AD8 C/BE0# AD7 VSS5/3 AD6 AD5 AD4 AD3 AD2 VDD5/3 DVSS3 DVDD3 AD1 AD0 N.C. PME# VSS5/3 VSS5 MEMWE# MEMOE# MEMCS# EECS N.C. MD7 MD6 VDD5 MD5 MD4
108
105 5
100 10
95 15
90 20
85 25
80 30
75 35 36 37 72 45 60 65 50 70 40 55 73
VDD5/3 REQ# GNT# PCICLK RST# INTA# VSS5/3 DVDD3 DVSS3 AVSS3 AVDD3 TPBIAS0 TPA0 TPA0# TPB0 TPB0# AVDD3 AVSS3 AVSS3 AVDD3 TPBIAS1 TPA1 TPA1# TPB1 TPB1# AVDD3 AVSS3 AVSS3 AVDD3 TPBIAS2 TPA2 TPA2# TPB2 TPB2# AVDD3 AVSS3
CPS R0 AVDD3 AVSS3 RF FIL AVDD3 AVSS3 CLK DVSS3 DVDD3 CSCLK VSS5 TEST MA0 MA1 MA2 MA3 MA4 MA5 VDD5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 VSS5 MA13 MA14 MA15 MD0 MD1 MD2 MD3
(FPT-144P-M08)
3
MB86613
2. FBGA-176
N.C.
N.C.
AVSS3
AVSS3
CSCLK
MA1
MA5
MA8
VSS5
MA15
MD3
N.C.
P
N.C.
AVSS3
N.C.
AVDD3
AVDD3
DVDD3
MA0
VDD5
MA9
VSS3
MD0
N.C.
N.C.
N.C.
N
TPB2
TPB2#
N.C.
RO
FIL
DVSS3
TEST
MA6
MA10
MA13
MD2
N.C.
N.C.
N.C.
M
TPA2
TPA2#
N.C.
AVDD3
RF
CLK
MA2
MA7
MA11
MD1
N.C.
MD5
VDD5
MD6
L
AVSS3
AVDD3 TPBIAS2
N.C.
CPS
VSS5
MA3
MA4
MA14
MD4
MD7
N.C.
EECS
MEMCS#
K
TPB1
TPB1#
AVDD3
AVSS3
N.C.
PME#
MEMOE# MEMWE#
VSS5
VSS5/3
J
TPBIAS1
TPA1
TPA1#
N.C.
AVDD3 (TOP VIEW)
DVSS3
DVDD3
N.C.
AD0
AD1
H
AVDD3
TPB0#
TPB0
AVSS3
AVSS3
VDD5/3
AD5
AD4
AD3
AD2
G
TPA0#
TPA0
TPBIAS0 AVDD3
N.C.
VSS5/3
C/BE0#
AD7
VSS5/3
AD6
F
AVSS3
DVSS3
DVDD3
VSS5/3
GNT#
VSS5/3
DVDD3
DVSS3
VSS5/3
VDD5/3
AD13
AD10
AD9
AD8
E
INTA#
RST#
PCICLK
N.C.
AD29
C/BE3#
AD22
AD19
TRDY#
PERR#
N.C.
AD14
AD12
AD11
D
REQ#
VDD5/3
N.C.
AD30
AD26
IDSEL
AD22
AD16
IRDY#
STOP#
C/BE1#
N.C.
N.C.
AD15
C
N.C.
N.C.
N.C.
AD28
AD25
VSS5/3
AD20
AD17
FRAME# VSS5/3
PAR
N.C.
N.C.
N.C.
B
N.C. 14 13
AD31 12
AD27 11
AD24 10
AD23 9
VDD5/3 8
AD18 7
C/BE2# 6
DEVSEL # 5
SERR# 4
N.C. 3
N.C. 2 1
A
(BGA-176P-M02)
4
MB86613
s PIN LIST
1. LQFP-144
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O I/O I/O I/O Pin name AD15 AD14 AD13 AD12 AD11 VSS5/3 AD10 AD9 AD8 C/BE0# AD7 VSS5/3 AD6 AD5 AD4 AD3 AD2 VDD5/3 DVSS3 DVDD3 AD1 AD0 N.C PME# VSS5/3 VSS5 MEMWE# MEMOE# MEMCS# EECS N.C MD7 MD6 VDD5 MD5 Supply Voltage (V) 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5 5 5 5 5 5 5 Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O O I I I I O Pin name MD4 MD3 MD2 MD1 MD0 MA15 MA14 MA13 VSS5 MA12 MA11 MA10 MA9 MA8 MA7 MA6 VDD5 MA5 MA4 MA3 MA2 MA1 MA0 TEST VSS5 CSCLK DVDD3 DVSS3 CLK AVSS3 AVDD3 FIL RF AVSS3 AVDD3 Supply Voltage (V) 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5/3.3 5/3.3 3.3 3.3 (Continued) 5
MB86613
(Continued)
Pin No. 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 6 I/O O I I/O I/O I/O I/O O I/O I/O I/O I/O O I/O I/O I/O I/O O OD I I I O Pin name R0 CPS AVSS3 AVDD3 TPB2# TPB2 TPA2# TPA2 TPBIAS2 AVDD3 AVSS3 AVSS3 AVDD3 TPB1# TPB1 TPA1# TPA1 TPBIAS1 AVDD3 AVSS3 AVSS3 AVDD3 TPB0# TPB0 TPA0# TPA0 TPBIAS0 AVDD3 AVSS3 DVSS3 DVDD3 VSS5/3 INTA# RST# PCICLK GNT# REQ# Supply Voltage (V) 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 Pin No. 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O OD I/O I/O Pin name VDD5/3 AD31 AD30 AD29 AD28 AD27 VSS5/3 AD26 AD25 AD24 C/BE3# IDSEL VSS5/3 AD23 AD22 AD21 AD20 VDD5/3 DVDD3 DVSS3 AD19 AD18 AD17 AD16 VSS5/3 C/BE2# FRAME# IRDY# TRDY# DEVSEL# VSS5/3 STOP# PERR# SERR# PAR C/BE1# VDD5/3 Supply Voltage (V) 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3
MB86613
2. FBGA-176
Ball No. B1 B2 D4 C2 C1 D3 E4 D2 D1 F5 E3 E2 E1 F4 F3 F2 F1 G4 G3 G2 G1 G5 H5 H4 H1 H2 H3 J5 J1 J2 J3 J4 K1 K2 K3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O OD O O O O Pin name N.C. N.C. N.C. N.C. AD15 AD14 AD13 AD12 AD11 VSS5/3 AD10 AD9 AD8 C/BE0# AD7 VSS5/3 AD6 AD5 AD4 AD3 AD2 VDD5/3 DVSS3 DVDD3 AD1 AD0 N.C PME# VSS5/3 VSS5 MEMWE# MEMOE# MEMCS# EECS N.C. Supply Voltage (V) 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5 5 5 5 Ball No. K4 L1 L2 L3 K5 M1 M2 M3 N1 P2 N2 L4 N3 P3 M4 L5 N4 P4 K6 M5 N5 P5 L6 M6 N6 P6 L7 M7 N7 P7 K7 K8 L8 P8 N8 I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O O Pin name MD7 MD6 VDD5 MD5 MD4 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. MD3 MD2 MD1 MD0 MA15 MA14 MA13 VSS5 MA12 MA11 MA10 MA9 MA8 MA7 MA6 VDD5 MA5 MA4 MA3 MA2 MA1 MA0 Supply Voltage (V) 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
(Continued)
7
MB86613
Supply Voltage (V) 5 5/3.3 5/3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 Supply Voltage (V) 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 (Continued)
Ball No. M8 K9 P9 N9 M9 L9 P10 N10 M10 L10 P11 N11 M11 K10 P12 N12 M12 P13 N14 N13 L11 M13 M14 L12 K11 L13 L14 J10 K12 K13 K14 J11 J12 J13 J14
I/O I I I I O O I I/O I/O I/O I/O O I/O I/O
Pin name TEST VSS5 CSCLK DVDD3 DVSS3 CLK AVSS3 AVDD3 FIL RF AVSS3 AVDD3 R0 CPS N.C. N.C. N.C. N.C. N.C. AVSS3 AVDD3 TPB2# TPB2 N.C. N.C. TPA2# TPA2 N.C. TPBIAS2 AVDD3 AVSS3 AVSS3 AVDD3 TPB1# TPB1
Ball No. H11 H12 H13 H14 H10 G10 G11 G14 G13 G12 F10 F14 F13 F12 F11 E14 E13 E12 E11 D14 D13 D12 E10 C14 C13 C12 B14 A13 B13 D11 B12 A12 C11 D10 B11
I/O I/O I/O O I/O I/O I/O I/O O OD I I I O I/O I/O I/O I/O
Pin name N.C. TPA#1 TPA1 TPBIAS1 AVDD3 AVSS3 AVSS3 AVDD3 TPB0# TPB0 N.C. TPA0# TPA0 TPBIAS0 AVDD3 AVSS3 DVSS3 DVDD3 VSS5/3 INTA# RST# PCICLK GNT# REQ# VDD5/3 N.C. N.C. N.C. N.C. N.C. N.C. AD31 AD30 AD29 AD28
8
MB86613
(Continued)
Ball No. A11 E9 C10 B10 A10 D9 C9 B9 A9 D8 C8 B8 A8 E8 E7 D7 A7 B7 I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O Pin name AD27 VSS5/3 AD26 AD25 AD24 C/BE3# IDSEL VSS5/3 AD23 AD22 AD21 AD20 VDD5/3 DVDD3 DVSS3 AD19 AD18 AD17 Supply Voltage (V) 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 Ball No. C7 E6 A6 B6 C6 D6 A5 B5 C5 D5 A4 B4 C4 E5 A3 B3 C3 A2 I/O I/O I/O I/O I/O I/O I/O I/O I/O OD I/O I/O Pin name AD16 VSS5/3 C/BE2# FRAME# IRDY# TRDY# DEVSEL# VSS5/3 STOP# PERR# SERR# PAR C/BE1# VDD5/3 N.C. N.C. N.C. N.C. Supply Voltage (V) 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3 5/3.3
9
MB86613
s PIN DESCRIPTION
PCI I/F
AD31 to AD0 C/BE3# to C/BE0# PCICLK RST# PAR FRAME# IRDY# TRDY# STOP# IDSEL DEVSEL# REQ# GNT# PERR# SERR# INTA#
TPA2 to TPA0 TPB2 to TPB0 TPA2# to TPA0# TPB2# to TPB0# 1394 I/F TPBIAS2 to TPBIAS0 CPS RO
CLK RF FIL
Internal PLL
CSCLK
8 kHz
TEST PME#
MA15 to MA0 MD7 to MD0 MEMWE# MEMORY I/F MEMOE# MEMCS# EECS
Output pins of MB86613
10
MB86613
1. PCI Interface Pin Description
Pin name AD31 to AD0 C/BE3# to C/BE0# PCICLK RST# PAR FRAME# IRDY# TRDY# STOP# IDSEL I/O I/O I/O I I I/O I/O I/O I/O I/O I Function 32-bit data/address multiplexed signal Bus-command and byte-enable multiplexed signal PCI bus clock input pin (Up to 33 MHz) System reset input pin Even parity bit for AD31:0 and C/BE3:0. Enabled one PCI clock signal after address phase. Signal indicating that the bus is being driven by the master. Master data ready signal Target data ready signal Target-to-master data transfer stop request signal Chip select signal for accessing the configuration register During target operation: Output signal indicating that the this device has been selected. During master operation: Input signal indicating that the device connected to the PCI bus has been selected. Output signal requesting the bus arbiter for using the PCI bus Input signal for bus arbiter's response to REQ# Data parity error I/O signal Address parity error I/O signal Interrupt output signal Power supply request signal in power save mode
DEVSEL#
I/O
REQ# GNT# PERR# SERR# INTA# PME#
O I I/O OD OD OD
2. Memory Interface Pin Description
Pin name MA15 to MA0 MD7 to MD0 MEMWE# MEMOE# MEMCS# EECS I/O O I/O O O O O Function Externally-connected EPROM (BIOS ROM) address signal Externally-connected EPROM (BIOS ROM) data signal Connect this pin to the WE pin on the externally-connected EPROM (BIOS ROM) Connect this pin to the OE pin on the externally-connected EPROM (BIOS ROM) Connect this pin to the CS pin on the externally-connected EPROM (BIOS ROM) Connect this pin to the CS pin on the externally-connected EEPROM (PCI configuration ROM)
11
MB86613
3. 1394 Interface Pin Description
Pin name TPA2 to TPA0 TPB2 to TPB0 TPA2# to TPA0# TPB2# to TPB0# TPBIAS2 to TPBIAS0 CPS RO I/O I/O I/O I/O I/O O I O Function Differential I/O positive terminal of 1394 bus port A Differential I/O positive terminal of 1394 bus port B Differential I/O negative terminal of 1394 bus port A Differential I/O negative terminal of 1394 bus port B 1394 bus bias voltage supply pin. For connecting a terminal resistor to TPBIAS and TPA/B, see " sCOMPONENT CONNECTION DIAGRAM 1. 1394 Ports". Cable power input pin Connect a 5.1 k resistor between the RO and GND pins. For details, see " sCOMPONENT CONNECTION DIAGRAM 1. 1394 Ports".
4. Internal PLL Pin Description
Pin name CLK RF I/O I O Internal PLL clock input pin. Input a 24.576 MHz clock signal. Connect a 5.6 k resistor between the RO and GND pins. For details, see " sCOMPONENT CONNECTION DIAGRAM 2. Filter Circuit". Filter circuit connection pin. For connecting the filter circuit, see " sCOMPONENT CONNECTION DIAGRAM 2. Filter Circuit". Function
FIL
O
5. Miscellaneous Pin Description
Pin name I/O Function This pin inputs the trigger signal for sending a cycle start packet during cycle master operation. Input an 8 kHz (125 s) clock signal. If the CLK pin is not used (with no Link Control. cycle Source bit set), however, connect this pin to GND. This pin in used for test mode. During normal operation, leave this pin connected to GND. Leave this pin unconnected.
CSCLK
I
TEST N.C.
I
12
MB86613
s BLOCK DIAGRAM
PCI/DMA
OHCI
1394
AR/IR-CPC LINK -Rx phys-req unit DMAC AT-CPC LINK -Tx IT-CPC PCI I/F CPC work memory (128B x 3) OpenHCI register (2048B) LINK core PHY FIF0 (6 KB)
slave
parallel ROM I/F
serial ROM I/F
Bus manager
13
MB86613
s BLOCK DESCRIPTION
* Parallel ROM I/F This block is the parallel port ROM interface to which EPROM (BIOS ROM) with a data width of 8 bits and that EEPROM (PCI configuration ROM) are connected which contains PCI subsystem ID and subsystem vendor ID information. For details, see " sCOMPONENT CONNECTION DIAGRAM 3. Memory Interface" * CPC (context program controller) This block analyzes context programs stored in host memory to store the packet to be sent out from host memory to the FIFO buffer or to store the received packet from the FIFO buffer to host memory (AR-CPC, IR-CPC). Upon reception of a physical request packet, this block analyzes the packet automatically for servicing the request (phys-req unit). * CPC work memory This block is work memory which stores context programs prepared in host memory or packet header information upon reception of a physical request packet. * OHCI register This block holds 2048 bytes of registers defined in the Open HCI Standard. * FIFO This block is a 6-KB FIFO buffer. This FIFO consists of a transmit-packet storage area (AT-FIFO and IT-FIFO) and a receive-packet storage area (AR-FIFO and IR-FIFO), each of which is freely addressable. * LINK-Rx This block stores the LINK-received, 1394-formatted packet in the FIFO buffer, with trailer data defined in the Open HCI Standard added. * LINK-Tx This block converts the packet stored in the FIFO buffer into the 1394 format and sends it to the LINK. * PCI I/F This block provides PCI bus protocol control. * PCI-DMAC This block issues a transfer request with the MB86613 serving as the bus master. * PCI-slave This block responds to the register access from the bus master. * LINK core This block generates data CRC and header CRC, transmits the selfID packet, and controls packet transmission and reception. * PHY This block provides 1394 bus protocol control. * Bus manager This block manages the cycle timer, generates a variety of interrupts, and holds the bus management CSR.
14
MB86613
s ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage1 Input current1 Output current
1
Symbol at 5 V2 at 3 V3 VDD VI VO TST TOP
Rating Min. VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 -55 -40 Max. 6.0 4.0 VDD + 0.5 VDD + 0.5 +125 +125
Unit V V V C C
Storage temperature Operating junction temperature *1 : The voltages are bassed on VSS = 0 V.
*2 : The 5 V power supply is the voltage applied at the VDD5/3 and VDD5 power supply pins. *3 : The 3 V power supply is the voltage applied at the DVDD3 and AVDD3 power supply pins. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
15
MB86613
s RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage1 at 5 V2 at 3 V3 S1004 S4004
4
Symbol VDD5 VDD3
Value Min. 4.75 3.0 168 142 132 118 1.165 Max. 5.25 3.6 265 260 260 260 2.5155 2.5155 2.5155 1.08 0.5 0.315 0.8 0.55 0.5 +2 +4 70
Unit V
TPA/B arbitration Differential input voltage TPA/B TPA/B TPBias input voltage TPA/B S2004 TPA/B S100 VID
mV p-p diff
TPA/B S2004 TPA/B S4004 TPA/B S1004
VCM
0.935 0.523
V
Receiving input jitter
TPA/B TPA/B
S2004 S4004 S2004 S4004

ns
TPA/B S1004 Receiving input skew6 TPA/B TPA/B Output current
-2 -4 0
ns
TPBIAS pin MD pin
IO Ta
mA C
Operating ambient temperature *1 : Voltage values are based on Vss =0V.
*2 : The 5 V power supply is the voltage applied at the VDD5/3 and VDD5 power supply pins. *3 : The 3 V power supply is the voltage applied at the DVDD3 and AVDD3 power supply pins. *4 : During speed signaling *5 : With cable power feed, the value is 2.015 (V). *6 : Skew between TPA pin and TPB pin. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
16
MB86613
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(VDD = 4.75 to 5.25 V ( for 5 V) , VDD = 3.0 to 3.6 V ( for 3 V) , VSS = 0 V, Ta = 0 to + 70 C) Value Parameter Symbol Unit Min. Max. at 5 V1 Power supply voltage at 3 V2 IDD 50 200 (10) 3 mA
*1 : The 5 V power supply is the voltage applied at the VDD5/3 and VDD5 power supply pins. *2 : The 3 V power supply is the voltage applied at the DVDD3 and AVDD3 power supply pins. *3 : Supply current in sleep mode. (1) PCI Interface Parameter "H" level input voltage "L" level input voltage "H" level output voltage "L" level output voltage Input leak current Input pin capacitance Clock pin capacitance (2) PCI Interface Parameter "H" level input voltage "L" level input voltage "H" level output voltage "L" level output voltage Input leak current Input pin capacitance Clock pin capacitance Symbol VIH VIL VOH VOL IIH IIL CIN CCLK Condition IOH = -2.0 (mA) IOL = 3.0 (mA) VIN = 2.7 (V) VIN = 0.5 (V) Symbol VIH VIL VOH VOL IIL CIN CCLK Condition IOH = -0.5 (mA) IOL = 1.5 (mA) 0 < VIN < VDD3
(VDD = 3.0 to 3.6 V, Ta = 0 to + 70 C) Value Unit Min. Max. VDD3 x 0.5 VSS - 0.5 VDD3 x 0.9 5 VDD3 + 0.5 VDD3 x 0.3 VDD3 x 0.1 10 10 12 V V V V A pF pF
(VDD = 4.75 to 5.25 V, Ta = 0 to + 70 C) Value Unit Min. Max. 2.0 VSS - 0.5 2.4 5 VDD5 + 0.5 0.8 0.55 10 10 10 12 V V V V A A pF pF
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MB86613
(3) Memory Interface Parameter "H" level input voltage "L" level input voltage "H" level output voltage "L" level output voltage Input leak current1 Input pull-up/pull-down resistance2 *1 : For input at 3-state pin. *2 : Typical resistance value 50 k. (4) CLK, CSCLK Pins Parameter "H" level input voltage "L" level input voltage Input leak current Input pull-up/pull-down resistance Clock pin capacitance * : For input at 3-state pin. Symbol VIH VIL IIL RP CCLK Condition 0 < VIN < VDD3 VIH = VDD3 Value Min. VDD3 x 0.7 VSS -5 25 TBD Max. VDD3 + 0.3 VDD3 x 0.2 +5 200 TBD Unit V V A k pF Symbol VIH VIL VOH VOL IIH IIL RP Condition IOH = -4.0 (mA) IOL = 4.0 (mA) VIN = 2.7 (V) VIN = 0.5 (V) VIH = VDD5 Value Min. 2.0 VSS - 0.5 2.4 25 Max. VDD5 + 0.5 0.8 0.4 10 10 100 Unit V V V V A A k
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MB86613
(5) 1394 Interface Parameter Differential output voltage Common phase current Off state voltage Speed-signal drive current TPBIAS output voltage1 DS comparator offset voltage2 Arbitration comparator offset voltage2 Speed-signal comparator offset voltage3 Port status comparator offset voltage4 Schmitt trigger receiver threshold voltage for detection connection Comparator offset voltage for detecting cable power supply CPS pin input voltage Common input current Symbol VOD ICM VOFF VO VIT VITH VITL VIT VIT VIT+6 VIT-6 VIT VCPS IIC S200 S400 Condition 56 terminal Transceiver OFF Transceiver OFF S100 S200 S400 Value Min. 172 -0.81 -0.81 -2.53 -8.10 1.665 -30 89 -168 120 290 0.6 1.95 1.00 1.125 (7.5) 5 VSS -20 Max. 265 0.44 20 0.44 -4.84 -12.40 2.015 30 168 -89 180 380 1.0 2.40 1.45 1.275 (8.5) 5 VDD5 20 Unit mV mA mV mA mA mA V mV mV mV mV mV V V V V V A
*1 : When the TPBIAS supply is Off, the maximum value with cable connected is 0.4 V, and when the cable is not connected the maximum output voltage is VDD. * 2 : Electrical potential created between TPA and TPB pins. *3 : Electrical potential created between TPBIAS and TPA/B pins *4 : At a point midway between the TPB/TPB# pins. *5 : Cable supply voltage (VP) : voltage before division by 510 k to 91 k resistance *6 : VIT+ is the voltage before cable disconnection is detected. VIT- is the voltage after cable connection is detected.
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MB86613
2. AC Characteristics
(1) CLK Parameter Clock frequency Clock cycle time Clock pulse width Clock rise/fall time Symbol fC tCLF tCLCH, tCLCL tCR, tCF Condition 10 Value Min. 24.576 1 / fC 5 Max. Unit MHz s ns ns
tCLCH tCR 0. 7 VDD3 0. 3 VDD3
tCLF tCF
CLK
tCLCL
Note : The CLK pin is the pin used for input of the reference clock signal for the built-in PLL circuit. (2) CSCLK Parameter Clock frequency Clock cycle time Clock pulse width Clock rise/fall time Symbol fC tCLF tCLCH, tCLCL tCR, tCF Condition 50 Value Min. 8 1 / fC 5 Max. Unit kHz ms s ns
tCLCH tCR 0. 7 VDD3 0. 3 VDD3
tCLF tCF
CSCLK
tCLCL
20
MB86613
(3) PCICLK Parameter Clock frequency Clock cycle time Clock pulse width Clock rise/fall time Slew rate Symbol fC tCLF tCLCH, tCLCL tCR, tCF Condition Value Min. 30 11 1 Max. 33 Unit MHz ns ns ns V/ns
6 4
tCLCH tCR 2.0 (V)
tCLF tCF
0.8 (V)
PCICLK
tCLCL
(4) RST# Parameter Hold time after power stabilization Hold time after clock stabilization Symbol tRST tCLKHM Condition Value Min. 0 6 Max. Unit PCI CLK PCI CLK
PCICLK
tCLKHM
RST#
tRST
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MB86613
(5) Transceiver Parameter Transceiver rise time Transceiver fall time Sending output jitter Sending output skew Symbol TR TF Condition 10% to 90% 90% to 10% Value Min. Max. 1.2 1.2 0.15 0.10 Unit ns ns ns ns
* : Skew between TPA pin and TPB pin. (6) PCI Bus Parameter Input data setup time Input data hold time Data output delay time Output data verification time Output data valid time Symbol tDWSH tDWHM tRHDM tRLDM tVALID Condition Value Min. 7 (10) 1 (1) 2 (2) 2 Max. 11 (12) 28 Unit ns ns ns ns ns
PCICLK
tDWSH tDWHM
INPUT
tRHDM
OUTPUT
3-STATE OUTPUT
tRLDM tVALID
* : Between REQ# and GNT# pins. 22
MB86613
* Bus Master Write Operation
PCICLK
REQ#
GNT#
FRAME#
AD31 to AD0
ADDR
DATA
C/BE3# to C/BE0#
CMD
DATA
PAR
ADDR
DATA
IRDY#
DEVSEL#
TRDY#
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MB86613
* Bus Master Read Operation
PCICLK
REQ#
GNT#
FRAME#
AD31 to AD0
ADDR
DATA
C/BE3# to C/BE0#
CMD
BE
PAR
ADDR
DATA
IRDY#
DEVSEL#
TRDY#
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MB86613
* Slave Write Processing
PCICLK
FRAME#
AD31 to AD0
ADDR
DATA
C/BE3# to C/BE0#
CMD
BE
PAR
ADDR
DATA
IRDY#
DEVSEL#
TRDY#
STOP#
PERR#
SERR#
25
MB86613
* Slave Read Processing
PCICLK
FRAME#
AD31 to AD0
ADDR
DATA
C/BE3# to C/BE0#
CMD
BE
PAR
ADDR
DATA
IRDY#
DEVSEL#
TRDY#
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MB86613
* Bus Master Burst Read Processing
PCICLK
REQ#
GNT#
FRAME#
AD31 to AD0
ADDR
DATA DATA DATA DATA
C/BE3# to C/BE0#
CMD
BE
PAR
ADDR
DATA DATA DATA DATA
IRDY#
DEVSEL#
TRDY#
STOP#
27
MB86613
* Bus Master Burst Write Processing
PCICLK
REQ#
GNT#
FRAME#
AD31 to AD0
ADDR
DATA
DATA DATA DATA
C/BE3# to C/BE0#
CMD
BE
PAR
ADDR
DATA
DATA DATA DATA
IRDY#
DEVSEL#
TRDY#
STOP#
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MB86613
(7) Memory Interface * EPROM Parameter MEMCS# signal "L" level output time Input data definition time Input data hold time Write cycle time Address setup time Address hold time MEMWE# signal pulse width Symbol tMEMCS tDWSH tDWHM tWC tAWSM tAWHM tMEMWE Condition Value Min. 13 15 25 Max. 50 10 10 50 Unit ns ns ns ns ns ns ns
tWC
MA15 to MA0
VALID
MEMOE#
tMEMCS
MEMCS#
MD7 to MD01
tDWHM tDWSH
MEMME#
tAWSM tMEMWE tAWHM
MD7 to MD02
VALID
*1 : For EPROM read processing. *2 : For EPROM write processing. 29
MB86613
* EEPROM Parameter Clock cycle time CS signal setup time SK signal setup time CS signal "L" level output time Data output hold time ( for DO) Input data setup time ( for DI) Input data hold time (DI) CS signal hold time Status output definition time Symbol tSK tCSWSM tSKWSM tCS tRHDM tDWSM tDWHM tCSWHM tRLDM Condition Value Min. 1000 50 50 250 20 100 20 0 500 Max. Unit ns ns ns ns ns ns ns ns ns
EECS (CS)
tCSWSM tSKWSM tSK tCSWHM tCS
MA1 (SK)
tDWSM
tDWHM
MA0 (DI)
tRHDM
MD0 (DO)1
tRLDM
MD0 (DO)2
STATUS VALID
*1 : For EPROM read processing. *2 : For EPROM write processing.
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MB86613
s COMPONENT CONNECTION DIAGRAM
1. 1394 Port
cable power pair 510 k CPS 91 k
TPBIAS + 56 TPA+ TPA- TPB+ TPB- cable pair B cable pair A 56 - I F
56
56
250 pF
5.1 k
RO
5.1 k
31
MB86613
2. Filter Circuit
CLK
RF
FIL
24.576 MHz 5.6 k
390
3300 pF
3. Memory Interface
EPROM MD7 to MD0 MA15 to MA0 MEMWE# MEMOE# MEMCS# 8 16
D7 to D0 A15 to A0 WE# OE# CS#
2 EEPROM MD0 MA0 MA1 EECS
EEDO EEDI EECLK EECS
32
MB86613
s ORDERING INFORMATION
Part number MB86613PFV MB86613PBT Package 144-pin Plastic LQFP (FPT-144P-M08) 176-pin Plastic FBGA (BGA-176P-M02) Remark
33
MB86613
s PACKAGE DIMENSIONS
144-pin plastic LQFP (FPT-144P-M08)
22.000.30(.866.012)SQ 20.000.10(.787.004)SQ 1.70(.67)MAX (Mounting height)
73 72
108 109
0(0)MIN (STAND OFF)
17.50 (.686) REF INDEX
144 37
21.00 (.827) NOM
Details of "A" part 0.15(.006)
0.15(.006) 0.15(.006)MAX 0.40(.016)MAX "A"
LEAD No.
1
36
Details of "B" part
M
0.50(.0197)TYP
0.200.10 (.008.004)
0.08(.003)
0.150.05 (.006.002) 0 10
0.10(.004)
0.500.20(.020.008) "B"
C
1995 FUJITSU LIMITED F144019S-1C-2
Dimensions in mm (inches)
(Continued)
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MB86613
(Continued) 176-pin plastic FBGA (BGA-176P-M02)
12.000.10(.472.004)SQ
Note : The actual shape of corners may differ from the dimension.
+0.20 +.008
1.25 -0.10 .049 -.004 (Mounting height)
0.80(.031) TYP
10.40(.410)REF
0.10(.004)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 PNMLK JHGFEDCBA
C0.80(.031) INDEX 0.380.10(.015.004) (Stand off)
176-O0.450.10 (176-O.018.004)
0.08(.003)
M
C
1998 FUJITSU LIMITED B176002S-1C-1
Dimensions in mm (inches)
35
MB86613
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8588, Japan Tel: +81-44-754-3763 Fax: +81-44-754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, USA Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220
http://www.fmap.com.sg/
F0004 (c) FUJITSU LIMITED Printed in Japan

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